Advancements in semiconductor fabrication and manufacturing techniques have led to reduction in operating voltage levels. One of the main reasons for using lower operating voltage levels is to reduce the power consumption in semiconductor chips.
But in cases where a chip is interfaced with a bus operator according to a standard based on higher voltage levels, typically only the main bulk (core) of the chip is operated at a lower voltage level and its I/O interface is operated at higher voltage levels. In order to implement such a scheme, the chip translates high-voltage I/O signals to low-voltage core signals and low-voltage core signals to high-voltage I/O signals. A problem while translating low-voltage core signals to high-voltage I/O signals is of D.C. current. If a low-voltage signal is used to drive a device operating at higher voltage, it may cause the device to draw D.C. power, since it is neither fully off nor fully on.
Thus circuitry for translating voltage signals which can minimize D.C. current problems may be used. Also in this present technology, the core is typically manufactured at nanometer technology, which operates at approximately 1.0V. However, most I/O blocks are still operating at 3.3V. So to interface between the I/O blocks and the core a voltage translator that can operate with minimum power dissipation is typically used. Also, often high-speed I/O standards such as LVDS, HSTL etc. are supported to operate at clock speeds of 250 MHz or more and hence voltage translators must satisfy such high frequency requirements in these situations. FIG. 1 shows one such conventionally used translating circuitry. In this circuit, cross-coupled gates use regenerative feedback to quickly pull the output signal to full voltage.
A detailed description of the prior art circuitry shown in FIG. 1 is in U.S. Pat. No. 5,422,523, which is incorporated by reference. The circuitry of FIG. 1 is the embodiment shown in FIG. 6 of the referred patent. The output of inverter LV, working at low voltage (VDDL), is connected to the gate of NMOS 103. Consider the case when IN goes from 0 volts to VDDL, where VDDL is the core voltage which is to be converted to VDDH (I/O Voltage), NMOS 104 is ON which reduces the voltage at line 206. This makes PMOS 101 ON and the voltage at OUT is increased. The output of LV is 0 volts which makes NMOS 103 OFF. An increase in the voltage at OUT makes PMOS 102 less conducting, which further decreases voltage at 206. This cycle is repeated until the voltage at OUT rises to VDDH.
Similarly, when IN goes from VDDL to 0 volts, NMOS 104 goes OFF and NMOS 103 becomes ON, to pull down OUT. Reduction in voltage at OUT makes PMOS 102 slightly ON which in turn increases voltage at line 206. This decreases the conductivity of PMOS 101 leading to further reduction in voltage at OUT. This recursive feedback ultimately makes OUT equal to 0 volts.
This translator circuitry gives good results when the voltage difference between VDDH and VDDL is small, but starts malfunctioning and even fails completely when the difference between higher and lower supply voltages is large. For example FIG. 2 shows the simulation results of the prior art circuitry, for higher supply voltage VCC equal to 3.6V and lower supply voltage equal to 0.8V. In the figure output OUT of translating circuitry is shown for five different operating conditions (mentioned in FIG. 2 itself).
It can be seen that for case.1 (typical process corners), case.3 (fast process corners) and case.5 (nmos fast, pmos slow process corners) the output is acceptable but for case.4 (nmos slow and pos fast process corner) it gets distorted and for case.2 (both nmos and pmos slow process corners) there is no output (constant low).
A reason theorized for the failure of the circuit is the cross-coupled gates using regenerative feedbacks. In this circuit of FIG. 1, switching is initialized by the input signal IN and finally controlled and concluded by regenerative feedback. Switching initialization by the input IN typically has to endure long enough to ensure some threshold voltage reached at the nodes OUT and Net 206, before switching is handed over to regenerative feedback. If the initialization process is weak, then the translator may switch late or will not switch and the output ‘OUT’ will get distorted or stuck to one state (high or low).
The transition times and rise-rise and fall-fall delays may become worse when the difference between lower and higher supply is large say 0.8V to 3.6V. The situation of having a large difference between higher and lower supply voltages frequently arises in case of FPGAs because FPGAs are frequently used for various applications and are therefore interfaced with various devices operating at varied bus standards. Due to vast and diverse field of applications of FPGAs, it is often desirable to have their I/O interface circuits capable of being programmed to operate at various voltage levels. Here I/O operating voltage levels may range from 3.6 V to 1.1V. On the other hand the main bulk (core) operating voltage can be as low as 0.8 V.
To overcome these problems, US 2005/0162209 A1, which is incorporated by reference, describes a high-speed voltage translator shown in FIG. 3. However, the described translator may result in static power dissipation as all devices in the serial path of components 36, 42, 70 and 66, or the serial path of components 40, 44, 54 and 68 may be ON under certain conditions, resulting static power loss. Also the translator uses many PMOS devices, resulting in a larger silicon area.
In reference to the above problems, there is a need for a voltage translator that can translate a low core voltage (as low as 0.8V or lower) to a higher I/O voltage (from 1.V to 3.6V or higher) with improved transition times and delays and with reduced dissipation of static power.